AI Supercycle Hits the Power Wall

AI has a compute problem everyone talks about and a power problem everyone feels but doesn't really talk about. This is why companies like TSMC and NVIDIA find themselves at a critical moment of a what we will now call "the long evolution of AI". TSMC, often described as the "orchestrator of all AI accelerators", is undeniably central.

With knowledge work alone, consultants asking ChatGPT to write emails millions of times a day, token-processing demand could grow 20×, and once entertainment, robotics, and autonomous systems join in, that number could balloon 80×. Global AI semiconductor revenue is forecast to potentially make up 52% of the entire US$1 trillion semiconductor market by 2030.

So, the AI supercycle is real. It's moving fast. But it's also about to hit a "power wall" problem.

More chips deployed for AI requires more electricity, and that means more batteries on the grid – specifically Battery Energy Storage Systems (BESS). The advanced chips are scarce, facing supply constraints despite massive investment; but the batteries are getting cheaper. Somewhere in that tension is the real story of the next few years.

So the question isn't whether AI will scale anymore, but whether compute and power can scale together. If TSMC pushes advanced packaging like CoWoS and leading-edge capacity fast enough - and if grid storage (BESS) spreads to data-center sites with more NVIDIA GPUs racked up, things become more economical, the AI supercycle steps over the power wall.

If not, we get waitlists and interconnect queues for a very, very, long time...

Why all the fuss?

The focus on using less energy to move data faster is a necessary evolution for the data center industry. It addresses the critical bottlenecks of power, cooling, and cost, ensuring that the infrastructure supporting the digital world can scale sustainably to meet the exponential growth driven by AI and other data-intensive applications.

The push to move data within data centers with less energy and at faster speeds is critical because the explosive growth of AI (hence the supercycle) and large-scale computing is straining the limits of current data center power and cooling infrastructure. Simply adding more chips is no longer a sustainable path forward due to energy constraints, operational costs, and physical space limitations.

The Energy Challenge in Data Centers

Data centers are significant consumers of global energy. In 2020, data centers in Germany and China already accounted for 2.9% and 2.7% of respective countries' total electricity consumption, a trend that is expected to continue its rapid rise.

Morgan Stanley identifies energy as one of the key limitations to AI growth, alongside budget, chip capacity, and regulation. The primary driver of this increased demand is the massive computational power required for training and running AI models.

In particular, growth in AI is creating limitations tied to:

Energy Consumption: The power required for advanced chips (GPUs/ASICs) and moving vast amounts of data between them is immense. This leads to higher operational costs and a greater environmental footprint. This power demand requires solutions like high-voltage DC power delivery (e.g., 800V HVDC), creating opportunities for new power semiconductor technologies like GaN, with the data center GaN TAM potentially reaching US$1.2bn by 2030. SiC semiconductors also play a role in efficient power management within these high-demand environments.

Heat Generation: Increased power consumption generates
more heat, requiring more complex and costly cooling systems to maintain
optimal operating temperatures and prevent equipment failure.

Chip Capacity: In some global regions, the ability to manufacture and supply enough advanced chips is a constraint. Even with TSMC aggressively raising capex and expanding advanced packaging capacity like CoWoS (targeting 100kwpm by 2026), industry-wide demand for AI compute continues to outstrip supply, a situation likely to persist until around 2028. TSMC's significant pricing power and resilient margins reflect this dynamic and fund the necessary expansion. Interestingly, TSMC's capex intensity (capex/revenue) has been falling, a sign of efficiency even amid high investment...

Grid Stability: Integrating large-scale AI data centers, often alongside intermittent renewable energy sources, requires enhanced grid stability and flexibility. This is where BESS becomes crucial, offering the fastest responding power source to manage fluctuations. The demand for BESS is projected to grow rapidly, with a 22% CAGR expected between 2025-2030, reaching a market size potentially around US$40bn by 2030.

Shifting Focus from More Chips to Better Interconnects

To overcome these challenges, the industry is shifting its focus from merely increasing the number of processing chips to fundamentally re-architecting how data moves within the data center. The goal is to enhance data transmission speeds while simultaneously reducing power consumption.

Co-Packaged Optics (CPO):

A key technology enabling this shift is Co-Packaged Optics (CPO). CPO involves moving the optical components that transmit data via light much closer to the main processing and switching silicon (ASICs) and integrating them into the same package.

The CPO architectural change offers significant advantages:

Reduced Power Consumption: Traditional pluggable optical modules require separate Digital Signal Processor (DSP) chips. By placing the optics next to the switch ASIC, CPO shortens electrical pathways, potentially eliminating these DSPs and significantly reducing power. TSMC projects solutions like COUPE on substrate in CoWoS CPO could offer a 2x reduction in power and a 10x reduction in latency by 2026, with further improvements possible.

Enhanced Performance and Density: Shorter connections improve signal integrity, allowing higher data rates (1.6T and beyond) and bandwidth density. This helps scale operations without proportional increases in power and heat.
  
Lower Operational Costs: For large-scale data centers, power savings translate into significant operational expense reductions.

Advancements in Chip-Level Efficiency

Alongside improvements in data movement, chip manufacturers like TSMC are developing new solutions to enhance on-chip power efficiency. An example is TSMC's A16 node featuring backside power delivery , which reworks chip wiring for more efficient power delivery. This approach can improve performance-per-watt (power efficiency) by 15-20% for each node migration , representing what some call "Moore's Law 2.0" where energy efficiency becomes a key feature alongside transistor density.

The Battery Balancing Act

While compute efficiency is crucial, the sheer scale of AI necessitates more power infrastructure. Falling BESS prices are critical enablers. The price elasticity for ESS installation is high (around 2.5x), meaning that as battery costs decrease (driven largely by dominant Chinese LFP battery manufacturers), demand for ESS projects increases significantly due to improved project economics (IRR). Every 10% drop in battery ASP could potentially boost battery maker revenue by 13% due to this demand stimulus.

Scaling Compute and Power Together Defeats the Power Wall

The focus on using less energy to move data faster, coupled with more efficient chip designs and falling energy storage costs, is a necessary evolution. The AI supercycle's trajectory depends not just on producing more powerful chips – a challenge TSMC is tackling with massive investment in leading-edge nodes and advanced packaging – but also on solving the power equation. Technologies like CPO, advanced power semiconductors (GaN/SiC), backside power delivery on chips, and the rapidly scaling, increasingly cost-effective BESS market are all critical pieces.

This dynamic creates significant knock-on effects across the AI landscape:

Large Language Models (LLMs): The exponential growth in tokens processed, particularly for inference, directly translates into soaring demand for compute power. Power and chip supply constraints could increase the cost of training and deploying the largest LLMs, potentially slowing the pace of frontier model development or limiting widespread access. This pressure incentivizes research into more compute-efficient LLM architectures and techniques (like quantization or pruning) to deliver performance within tighter power budgets. The sheer scale projected suggests that inference, eventually making up 80% of cloud AI semi-demand by 2030, will drive the need for specialized, power-efficient hardware.

GPUs: While NVIDIA benefits massively from being the primary provider of AI training GPUs, the power wall is forcing a design evolution. Future GPUs, like the upcoming Rubin series, must balance higher performance (FLOPS) with improvements in performance-per-watt, aligning with the "Moore's Law 2.0" focus on efficiency. Furthermore, NVIDIA's ability to meet demand is directly tied to TSMC's advanced packaging (CoWoS) capacity, which remains a bottleneck despite rapid expansion. This supply constraint, coupled with high costs and power consumption, encourages customers to explore alternatives, potentially creating openings for competitors or accelerating the adoption of custom ASICs. NVIDIA's push into full rack solutions like the GB200 NVL72 also aims to provide more integrated, efficient systems but may concentrate supply chain pressure if not careful.

Meta & Hyperscalers: Companies like Meta, Google, AWS, and Microsoft are making staggering capital expenditures, increasingly directed towards AI infrastructure. Meta's capex intensity now even surpasses TSMC's, highlighting the massive investment required. Big spending is partly driving their development of custom AI ASICs (like Meta's MTIA, Google's TPU, AWS's Trainium/Inferentia). These custom chips offer a path to potentially lower TCO compared to general-purpose GPUs, optimize performance for specific workloads (especially LLM inference), improve power efficiency, and reduce reliance on a single supplier like NVIDIA. Managing power consumption and securing access to both cutting-edge chips and sufficient energy (potentially augmented by BESS) is a key strategic differentiator for these major players.

The path forward requires a holistic approach

The success of the AI supercycle hinges on the industry's ability to innovate not just in chip performance, but critically, in power efficiency and energy management from the silicon level up to the grid.

Source Material

Chan, C., Yen, D., Dai, D., Yeh, T., Wang, L. and Jia, E. (2025) Greater China Technology Semiconductors: Global AI Supply-chain Updates; Key Opportunities in Asia Semis. Morgan Stanley Investor Presentation, 17 October. Cited pages: 3, 9, 11, 29, 32.

CLSA (2025a) Figure 7: The resilience of TSMC's margins has been remarkable. In: Vajpayee, B. and Son, H. TSMC - HC O-PF (Supercycle?). CLSA Research Report, 20 October. Cited page: 7.

CLSA (2025b) Figure 8: TSMC's capex/revenue ratios have fallen, and seems set to fall further. In: Vajpayee, B. and Son, H. TSMC - HC O-PF (Supercycle?). CLSA Research Report, 20 October. Cited page: 7.

CLSA (2025c) Figure 73: ESS installation-demand elasticity is ~2.5x. In: Tse, H., Li, K., Chin, S. and Chan, F. Global battery (ESSential for the future Energy storage...). CLSA Research Report, 1 September. Cited page: 41.

Tse, H., Li, K., Chin, S. and Chan, F. (2025) Global battery (ESSential for the future Energy storage...). CLSA Research Report, 1 September. Cited pages: 3, 5, 7, 41.

Vajpayee, B. and Son, H. (2025) TSMC - HC O-PF (Supercycle?). CLSA Research Report, 20 October. Cited pages: 1, 4, 11.